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document no. u17344ee1v1ds00 data published: february 2005 v850e/cg3 tm cargate+ 32-bit flash microcontroller the information contained in this document is released in advance of the production cycle for the device. the parameters for the device may change before final productio n, or nec corporation may, at its own discretion, with- draw the device prior to production. ? nec corporation 2005 data sheet mos integrated circuit pd70f3178(a) description the v850e/cg3 ("cargate+") flash microcontroller, is a member of nec's v850 32-bit risc family, which match the performance gains attainable with risc -based controllers to the needs of embedded control applications. the v850 cpu offers easy pipeline handli ng and programming, resulting in compact code size comparable to 16-bit cisc cpus. the v850e/cg3 ("cargate+") is especially desi gned for the high performance requirements of sophisticated algorithms and calculations. it combines a powerful cpu-core with a 16-bit wide external memory interface and embedded flash. furthermore, it offers an excellent combination of general purpose peripheral functions, like serial communication interfaces (uart, clocked si and i2c) and measurement inputs (a/d converter), with dedicated can network support. thus equipped, the v850e/cg3 ("cargate+?) is idea lly suited for automotive applications, like can gateways. it is also an excellent choice for other applications where a combination of sophisticated peripheral functions and can network support is required. functions in detail are described in the following u ser?s manual. be sure to read these manual when you design your systems. v850e/cg3 cargate+ preliminary user?s manual: u16881ee1v0um00 32-bit risc cpu with harvard architecture 256 kb flash, 12 kb ram full-can interface: 5 channels serial interfaces: 6 channels - 3-wire mode: 3 channels - uart mode: 2 channels - i2c mode: 1 channel timers: 3 channels - 16-bit multi purpose timer/event counter: channels: 3 channels 10-bit resolution a/d converter: 4 channels non-multiplexed external bus interface (16-/8-bit data / 20-bit address) i/o lines: max. 80 power supply voltage range: - +4.3 v v dd5 +5.5 v frequency range: up to 32 mhz built-in low power saving mode built-in clock oscillator circuit with internal pll temperature range: - -40 c to +85 c package: - 100 lqfp, 0.5 mm pin-pitch (14 14 mm) ordering information device part number package rom ram fcan option operating temperature (t a ) v850e/cg3 pd70f3178(a) lqfp100 14 14 mm 256 kb flash 12 kb 5 channels -40c ~ +85c features
2 data sheet u17344ee1v1ds00 pd70f3178(a) internal block diagram afcan0 afcan1 afcan2 afcan3 afcan4 mirror mode uarta0 uarta1 csib0 csib1 csib2 interrupt controller nmi intp0 - intp10 x1 x2 mode0, mode1 reset clock generator cg pll regulator v dd v ss regc0, regc1 tip20, tip21 top20, top21 16-bit timer p2 tip10, tip11 top10, top11 16-bit timer p1 tip00, tip01 top00, top01 16-bit timer p0 internal peripheral bus 96 k flash 96 k flash 32 k flash 32 k flash pc barrel shifter system registers general registers alu 12 k ram 32 x 32 multiplier bus control unit cpu core v850e d0 to d15 a0 to a19 cs0, cs3, cs4 rd wr0, wr1 memc non-multiplexed 8-/16-bit bus i/f av ss av dd ani0-ani3 ports 10-bit adc 4 channels p00 to p02 pct0, pct1, pct4 pcs0, pcs3, pcs4 pdl0 to pdl15 pal0 to pal15 p40 to p47 p30 to p36 p20 to p27 p10 to p17 brg0 p70 to p73 pah0 to pan3 i2c ttrgp2 crxd0 ctxd0 crxd1 ctxd1 crxd2 ctxd2 crxd3 ctxd3 crxd4 ctxd4 rxda0 txda0 rxda1 txda1 sib0 sob0 sckb0 sib1 sob1 sckb1 sib2 sob2 sckb2 sdai0 scl0
3 data sheet u17344ee1v1ds00 pd70f3178(a) pin identification a0 to a19 : address bus pal0 to pal 15 port al d0 to d15 : data bus pcs0, pcs3, pcs4 : port cs ani0 to ani3 : analog input pct0, pct1, pct4 : port ct av dd : analog power supply pdl0 to pdl15 port pdl av ss : analog ground reset :reset crxd0 to crxd5 : can receive line input rxda0 to rxda1 : uart receive data input ctxd0 to ctxd4 : can transmit line output sckb0 , sckb1 , sckb2 : serial clock cv dd : clock generator power supply scl i2c clock cv ss : clock generator ground sda i2c data bvss 50 to bvss 53 ground for 5 v power supply sib0, sib1, sib2 : serial input vss 50 to vss 51 ground for 5 v power supply sob0, sob1, sob2 : serial output intp0 to intp10 external interrupt request tip00 to tip01, tip10 to tip11, tip20 to tic21 : timer input intpn0, intpn5, intp2n : interrupt request from peripherals top00 to top01, top10 to top11, top20 to top21 timer output mode0, mode1 : mode inpu ts txda0 to txda1 : transmit data output nmi : non-maskable interrupt request ttrgp2 timer trigger input p00 to p02 port 0 bv dd50 to bv dd53 : 5 v power supply p10 to p17 : port 1 v dd50 to v dd51 : 5 v power supply p20 to p27 : port 2 wr0 , wr1 write enable p30 to p36 : port 3 rd :read p40 to p47 : port 4 cs0 , cs3 , cs4 chip select p70 to p73 port 7 x1, x2 : crystal (main-osc) pah0 to pah3 : port ah
4 data sheet u17344ee1v1ds00 pd70f3178(a) pin configuration (top view) 100-pin plastic lqfp (fine pitch) (14 mm u 14 mm) av dd av ss p02 p01/intp0 p10/crxd0 p11/ctxd0 p12/crxd1 p13/ctxd1 p14/crxd2 p15/ctxd2 p40/sib0 p42/sckb0 bv ss50 bv dd50 p16/crxd3 p46/crxd4 p27/crxd5/intp10 p21/tip01/top01/intp4 ani0 ani1 ani2 pdl14/d14 pdl13/d13 pdl12/d12 pdl11/d11 pdl10/d10 v dd51 v ss51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 46 47 48 49 50 cargate+ 52 51 77 76 p41/sob0 p17/ctxd3 p47/ctxd4 p20/tip00/top00/intp3 p22/tip10/top10/intp5 p23/tip11/top11/intp6 p24/tip20/top20/intp7 p31/txda0 p30/rxda0/intp1 p33/txda1 p25/tip21/top21/intp8 p43/sib1 p44/sob1 p45/sckb1 p34/sib2 p35/sob2/sda0 p36/sckb2/scl0 v dd50 regc0 v ss50 bv ss51 bv dd51 p00/nmi x1 x2 reset pah3/a19 pah2/a18 pah1/a17 pah0/a16 pal15/a15 p32/rxda1/intp2 ani3 p26/trgp2/intp9 pdl15/d15 regc1 pdl9/d9 pdl8/d8 bv dd53 bv ss53 pdl7/d7 pdl6/d6 pdl5/d5/mode1 pdl4/d4 pdl3/d3 pdl2/d2 pdl1/d1 pdl0/d0 pal0/a0 pal1/a1 pal2/a2 pal3/a3 pal4/a4 pal5/a5 pal6/a6 pcs4/cs4 pcs3/cs3 mode0 pcs0/cs0 bv dd52 bv ss52 pct1/wr1 pct0/wr0 pct4/rd pal7/a7 pal8/a8 pal9/a9 pal10/a10 pal11/a11 pal12/a12 pal13/a13 pal14/a14
5 data sheet u17344ee1v1ds00 pd70f3178(a) table of contents 1. pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 i/o circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2. programming flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3. electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 general characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 3.5 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 3.6 peripheral function characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.7 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 4. package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5. recommended soldering conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6 data sheet u17344ee1v1ds00 pd70f3178(a) list of figures figure 1-1: pin i/o circuits.................................................................................................... ......... 14 figure 3-1: ceramic resonator or crystal resonator connection ................................................ 17 figure 3-2: ac test input/output waveform ................................................................................. 20 figure 3-3: ac test load condition .............................................................................................. 20 figure 3-4: sram read timing.................................................................................................... .21 figure 3-5: sram write timing ................................................................................................... .. 22 figure 3-6: reset timing ........................................................................................................ ....... 23 figure 3-7: interrupt timing .................................................................................................... ....... 24 figure 3-8: timer p characteristics ............................................................................................. .. 25 figure 3-9: csi slave mode characteristics.................................................................................. 26 figure 3-10: i2c timing ......................................................................................................... ........... 28 figure 3-11: analog input equivalent circuit ................................................................................... 2 9 figure 3-12: flash memory timing ................................................................................................ .. 30 figure 4-1: package drawing ..................................................................................................... ... 31
7 data sheet u17344ee1v1ds00 pd70f3178(a) list of tables table 1-1: pin functions........................................................................................................ ............ 9 table 1-2: non-port pins ........................................................................................................ ......... 12 table 3-1: absolute maximum ratings............................................................................................ 1 6 table 3-2: dc characteristics................................................................................................... ....... 19 table 3-3: reset timing ......................................................................................................... ......... 23 table 3-4: interrupt timing ..................................................................................................... ......... 24 table 3-5: timer p characteristics .............................................................................................. .... 25 table 3-6: csib master mode characteristics ................................................................................ 26 table 3-7: csib slave mode characteristics .................................................................................. 26 table 3-8: uart characteristics ................................................................................................. .... 27 table 3-9: characteristics i2c .................................................................................................. ........ 27 table 3-10: afcan characteristics............................................................................................... .... 28 table 3-11: a/d converter characteristics ....................................................................................... .29 table 3-12: flash memory characteristics ........................................................................................ 30 table 3-13: flash memory characteristics ........................................................................................ 30 table 5-1: soldering conditions ................................................................................................. ..... 32
8 data sheet u17344ee1v1ds00 pd70f3178(a)
9 data sheet u17344ee1v1ds00 pd70f3178(a) 1. pin functions (1) port pins table 1-1: pin functions (1/3) port i/o function alternate p00 i/o port 0 3-bit input/output port nmi (i) p01 intp0 (i) p02 p10 i/o port 1 8-bit input/output port crxd0 (i) p11 ctxd0 (o) p12 crxd1 (i) p13 ctxd1 (o) p14 crxd2 (i) p15 ctxd2 (o) p16 crxd3 (i) p17 ctxd3 (o) p20 i/o port 2 8-bit input/output port top00 (o) tip00 (i) intp3 (i) crxd4 (i) p21 intp4 (i) top0 1 (o) tip01 (i) p22 intp5 (i) top1 0 (o) tip10 (i) p23 intp6 (i) top1 1 (o) tip11 (i) p24 intp7 (i) top2 0 (o) tip20 (i) p25 intp8 (i) top2 1 (o) tip21 (i) p26 ttrgp2 (i) intp9 (i) p27 intp10 (i) p30 i/o port 3 7-bit input/output port rxda0 (i) intp1 (i) p31 txda0 (o) p32 rxda1 (i) intp2 (i) p33 txda1 (o) p34 sib2 (i) p35 sdao0 (o) sdai0 (i) sob2 (o) p36 sclo0 (o) sckib2 (i) scli0 (i) sckob2 (o) p40 i/o port 4 8-bit input/output port sib0 (i) p41 sob0 (o) p42 sckib0 (i) sckob0 (o) p43 sib1 (i) p44 sob1 (o) p45 sckib1 (i) sckob1 (o) p46 crxd4 (i) p47 ctxd4 (o)
10 data sheet u17344ee1v1ds00 pd70f3178(a) pa h 0 i/o port pah 4-bit input/output a16 (o) pah1 a17 (o) pah2 a18 (o) pah3 a19 (o) pa l 0 i/o port pal 16-bit input/output a0 (o) pa l 1 a 1 ( o ) pa l 2 a 2 ( o ) pa l 3 a 3 ( o ) pa l 4 a 4 ( o ) pa l 5 a 5 ( o ) pa l 6 a 6 ( o ) pa l 7 a 7 ( o ) pa l 8 a 8 ( o ) pa l 9 a 9 ( o ) pal10 a10 (o) pal11 a11 (o) pal12 a12 (o) pal13 a13 (o) pal14 a14 (o) pal15 a15 (o) pcs0 i/o port pcs 3-bit input/output cs0 (o) pcs3 cs3 (o) pcs4 cs4 (o) pct0 i/o port pct 3-bit input/output wr0 (o) pct1 wr1 (o) pct4 rd (o) table 1-1: pin functions (2/3) port i/o function alternate
11 data sheet u17344ee1v1ds00 pd70f3178(a) pdl0 i/o port pdl 16-bit input/output do0 (o) di0 (i) pdl1 do1 (o) di1 (i) pdl2 do2 (o) di2 (i) pdl3 do3 (o) di3 (i) pdl4 di4 (i) do4 (o) pdl5 di5 (i) do5 (o) mode1 (i) pdl6 di6 (i) do6 (o) pdl7 di7 (i) do7 (o) pdl8 do8 (o) di8 (i) pdl9 do9 (o) di9 (i) pdl10 di10 (i) do10 (o) pdl11 di11 (i) do11 (o) pdl12 do12 (o) di12 (i) pdl13 do13 (o) di13 (i) pdl14 di14 (i) do14 (o) pdl15 di15 (i) do15 (o) table 1-1: pin functions (3/3) port i/o function alternate
12 data sheet u17344ee1v1ds00 pd70f3178(a) (2) non-port pins table 1-2: non-port pins (1/2) pin name i/o function port a0 - a15 o address bus of external bus pa l 0 - pa l 1 5 a16 - a19 o pah0 -pah3 ain0 - ain3 i analog input for a/d converter crxd0 i serial receive data input for afcan0 to afcan4 p10 crxd1 i p12 crxd2 i p14 crxd3 i p16 crxd4 i p46 crxd5 i additional receive input for mirror mode p20 cs0 o chip select output for external bus pcs0 cs3 opcs3 cs4 opcs4 ctxd0 o serial transmit data for afcan0 to afcan4 p11 ctxd1 o p13 ctxd2 o p15 ctxd3 o p17 ctxd4 o p47 d0 - d15 i/o data bus of external bus pdl0 - pdl15 intp0 i external interrupt request p01 intp1 i p30 intp2 i p32 intp3 i p20 intp4 i p21 intp5 i p22 intp6 i p23 intp7 i p24 intp8 i p25 intp9 i p26 intp10 i p27 nmi i non maskable interrupt p00 rd o read strobe signal pct4 rxda0 i serial receive data uarta0 & uarta1 p30 rxda1 i p32 sckb0 i/o serial clock i/o from csib0 - csib2 p42 sckb1 i/o p45 sckb2 i/o p36 scl0 i/o serial clock line i2c p36 sdai0 i/o serial data line i2c p35
13 data sheet u17344ee1v1ds00 pd70f3178(a) sib0 i serial data input csib0 - csib2 p40 sib1 i p43 sib2 i p34 sob0 o serial data output csib0- csib2 p41 sob1 o p44 sob2 o p35 tip00 i capture input 0-1 timer p0 - timer p2 p20 tip01 i p21 tip10 i p22 tip11 i p23 tip20 i p24 tip21 i p25 top00 o compare output 0-1 timer p0 - timer p2 p20 top01 o p21 top10 o p22 top11 o p23 top20 o p24 top21 o p25 ttrgp2 i timer trigger input timer p2 p26 txda0 o serial transmit data output uarta0 - uarta1 p31 txda1 o p33 wr0 o write strobe signal for external bus pct0 wr1 opct1 av dd ? 5 v power supply adc ? av ss ? gnd potential for 5 v power supply adc ? v dd50 -v dd51 ? 5 v power supply ? bv dd50 -bv dd53 ?? v ss50 -v ss50 ? gnd potential for 5 v power supply ? bv ss50 -bv ss53 ?? mode i specifies operation mode ? mode1 i pdl5 regc0 ? connection of regulator stabilization capacitance ? regc1 ? ? reset i system reset input ? x1 i connection of external oscillator ? x2 0 ? all v dd5 pins have to be connected to each other. on each pin of v dd5 , a capacitor containing a very low serial impedance has to be attached as tight as possible to the pin. table 1-2: non-port pins (2/2) pin name i/o function port
14 data sheet u17344ee1v1ds00 pd70f3178(a) 1.1 i/o circuits figure 1-1: pin i/o circuits type 5 data output disable input enable v dd p-ch in/out n -ch type 5-k data output disable v p-ch n-ch in/out dd v ss input enable type 9-c p-ch n-ch input enable + - v ref in comparator (threshold voltage) av ss type 2 in
15 data sheet u17344ee1v1ds00 pd70f3178(a) 2. programming flash memory the device pd70f3178(a) supports the programming of the internal flash in two ways: either by using the flash pro4 programming tool or by performing self-programming using software functions and i/o communications. for programming details about both methods, see th e user?s manual. for timing characteristics about the initial programming using flash pro4 and some more electrical data about the flash memory, see 3.7 "flash memory" on page 30.
16 data sheet u17344ee1v1ds00 pd70f3178(a) 3. electrical specifications all electrical parameters which are shown in the following tables are representing target values. 3.1 absolute maximum ratings (t a = 25c, v ss5 = 0 v) note: v ia is the voltage applied to the analog input pins p73?p70 remark: v dd5 is the supply voltage for the internal voltage regulators applied to pins v dd5x . a vdd is the supply and reference voltage for analog part of the a/d converter bv dd5 is the supply voltage for the i/o buffers applied to pins bv dd5x v ss5 is the ground for the internal logic applied to pins v ss5x a vss is the ground for the analog part of the a/d converter bv ss5 is the ground for the i/o buffers applied to pins bv ss5x table 3-1: absolute maximum ratings parameter symbol test conditions ratings unit supply voltage v dd5 -0.5 ~ +6.5 v av dd -0.5 ~ +6.5 v bv dd5 -0.5 ~ +6.5 v bv ss5 -0.5 ~ +0.5 v av ss -0.5 ~ +0.5 v input voltage v i4 v i4 < bv dd5 + 0.5 v -0.5 ~ + 6.5 v v ia note v ia < av dd + 0.5 v -0.5 ~ + 6.5 v output current low 1 pin i ol4 4.0 ma all pins i ola 50 ma output current high 1 pin i oh4 -4.0 ma all pins i oha -50 ma output voltage v o v o < bv dd5 +0.5 v -0.5 ~ +6.5 v operating temperature (ambient) t opr -40 ~ +85 c storage temperature t stgb -40 ~ +125 c
17 data sheet u17344ee1v1ds00 pd70f3178(a) 3.2 general characteristics 3.2.1 recommended main oscillator circuit figure 3-1: ceramic resonator or crystal resonator connection note: values of c 1 , c 2 and r depend on the used crystal or resonator and must be specified in cooperation with resonator manufacturer. 3.2.2 oscillator characteristics (t a = -40 ~ +85c, v dd5 = bv dd5 = 4.3 v ~ 5.5 v, v ss5 = bv ss5 = 0 v) note: t ost depends on the external crystal and the correct selection of c1, c2 and r. remark: this value is valid only for crystal operation. 3.2.3 peripheral pll characteristics (t a = -40 ~ +85c, v dd5 = bv dd = 4.3 v ~ 5.5 v, v ss5 = bv ss5 = 0 v) note: f osc is the oscillator frequency. parameter symbol test conditions min. typ. max. unit oscillation stabilization time t ost osc mode 16 note ms parameter symbol test conditions min. typ. max. unit pll start-up time t pst osc mode 4800/f osc note s x2 x1 c2 c1 r
18 data sheet u17344ee1v1ds00 pd70f3178(a) 3.2.4 i/o capacitances (t a = -40 ~ +85c, v dd5 = bv dd5 = 4.3 v ~ 5.5 v, v ss5 = bv ss5 = 0 v) 3.2.5 recommended capacitor values for regc the recommended capacitor value for regc0 and regc1 is 4.7 f. remarks: 1. nec recommends to use a second capacitor with 100 nf in parallel to reduce distur- bances with high frequencies. 2. the terminals regc0 and regc1 must not be connected to each other. 3.3 operating conditions 3.3.1 cpu clock (t a = -40 ~ +85c, v dd5 = bv dd5 = av dd = 4.3 v ~ 5.5 v, v ss5 = bv ss5 = av ss = 0 v) notes: 1. c 1 is the external capacitance connected to pin regc0 2. c 2 is the external capacitance connected to pin regc1 parameter symbol test conditions min. typ. max. unit input capacitance c i f c = 1 mhz unmeasured pins returned to 0 v 10 pf input/output capacitance c io 10 pf output capacitance c o 10 pf clock mode operation mode inside operation clock frequency [mhz] osc mode, pll off all modes c 1 note 1 = c 2 note 2 = 4.7 f 4 to 6 osc mode, pll u 4 20 to 24 osc mode, pll u 832
19 data sheet u17344ee1v1ds00 pd70f3178(a) 3.4 dc characteristics ( t a = -40 ~ +85c, v dd5 = bv dd5 =av dd = 4.3 v ~ 5.5 v, v ss5 = bv ss5 = av ss = 0 v) notes: 1. pin group 1 is pal, pah, pdl, pcs, pct 2. pin group 2 is p0, p1, p2, p3, p4, p7, mode, reset remark: these values are without consumption of i/o-pins table 3-2: dc characteristics parameter symbol test conditions min. typ. max. unit input voltage high v ih1 pin group 1 note 1 0.7 bv dd5 bv dd5 v input voltage low v il1 0 0.3 bv dd5 v input voltage high v ih1 pin group 2 note 2 0.7 bv dd5 bv dd5 v input voltage low v il1 0 0.3 bv dd5 v p73?p70 input voltage high v iha 0.7 av dd av dd v p73?p70 input voltage low v ila 0 0.3 av dd v output voltage high v oh i oh = -3.0 ma bv dd5 - 1 v output voltage low v ol i ol = 3.0 ma 0.4 v input leakage current high i lih v i = v dd5x -3 a input leakage current low i lil v i = 0 v 3a p73?p70 input leakage current high i liha v ia = av dd -3 a p73?p70 input leakage current low i lila v ia = 0 v 3a supply current i dd10 operating (f cpu = 32 mhz) pll: on 74 110 ma i dd11 operating (f cpu = 24 mhz) pll: on 57 90 ma i dd20 halt mode (f pll = 32 mhz) pll: on 45 70 ma i dd21 halt mode (f pll = 24 mhz) pll: on 35 55 ma i dd30 idle mode (f pll = 32 mhz) pll: on 2.6 4 ma i dd31 idle mode (f pll = 24 mhz) pll: on 2.6 4 ma i dd5 stop 30 200 a
20 data sheet u17344ee1v1ds00 pd70f3178(a) 3.5 ac characteristics t a = -40~ +85c, bv dd5 = v dd5 = av dd = 4.3v~5.5v, bv ss5 = v ss5 = a vss5 = 0v, output pin load capacitance: c l = 50 pf 3.5.1 ac test input/output waveform figure 3-2: ac test input/output waveform 3.5.2 ac test load condition figure 3-3: ac test load condition 3.5.3 clock ac characteristics parameter symbol test conditions min. typ. max. unit x1, x2 oscillator frequency f osc osc mode; pll u 4 46 mhz pll u 84 4mhz test points 0.7 bv dd5x 0.3 bv dd5x bv dd5x 0 v dut load on test c l = 50 pf
21 data sheet u17344ee1v1ds00 pd70f3178(a) 3.5.4 external memory access read timing note: t: 1 / f cpu (= frequency of system clock) i : number of idle states specified by bcc register w t : total number of waits, w t = w as +w d w as : number of waits specified by asc register w d : number of waits specifie d by dwc1, dwc2 register figure 3-4: sram read timing parameter symbol conditions min. max unit data input set up time (vs. address) <10> t said (2+w t )t - 45 ns data input set up time (vs. rd p )<11> t srdid (1.5+w d )t - 40 ns rd low level width <12> t wrdl (1.5+w d )t - 15 ns rd high level width <13> t wrdh (0.5+w as + it - 13 ns address, csn rd delay time <14> t dard (0.5+w as )t - 20 ns rd address delay time <15> t drda it - 15 ns data input hold time (vs. rd n )<16> t hrdid 0ns rd data output delay time <17> t drdod (0.5+i)t - 35 ns a0-a19 cs0 cs3 cs4 (output) (output) wr0 wr1 (output) rd (i/o) d0-d15 <13> <12> <15> <16> <17> <11> <14> <10>
22 data sheet u17344ee1v1ds00 pd70f3178(a) 3.5.5 external memory access write timing note: t : 1 / f cpu (= frequency of system clock) i : number of idle states specified by bcc register w t : total number of waits, w t = w as +w d w as : number of waits specified by asc register w d : number of waits specifie d by dwc1, dwc2 register figure 3-5: sram write timing parameter symbol conditions min. max. unit address, csn wr0 , wr1 delay time <20> t dawr (0.5+w as )t - 25 ns address set up (vs. wr0 , wr1 n )<21> t sawr (1.5+w t )t - 20 ns wr0 , wr1 address delay time <22> t dwra (0.5+i)t - 15 ns wr0 , wr1 high level width <23> t wwrh (1+ i +w as )t - 15 ns wr0 , wr1 low level width <24> t wwrl (1+w d )t - 15 ns data output set up time (vs. wr0 , wr1 n )<25> t sodwr (0.5+w t )t - 25 ns data output hold time (vs. wr0 , wr1 n )<26> t hwrod (0.5+i)t - 20 ns a0-a19 cs0 cs3 cs4 (output) (output) wr0 wr1 (output) rd (i/o) d0-d15 (i/o) d0-d15 write write read write <26> <25> <23> <20> <24> <21> <22>
23 data sheet u17344ee1v1ds00 pd70f3178(a) 3.5.6 reset (power up/down sequence) figure 3-6: reset timing table 3-3: reset timing parameter symbol test conditions min. max. unit reset high-level width t wrsh 500 ns reset low-level width t wrsl0 stop mode release, osc mode t ost ms t wrsl1 except stop mode release & power up 1.5 ms reset hold time t dvrr osc mode on power-on t wrslx ms reset setup time t dvrf osc mode on power-off 0 ns reset t dvrr t dvrf t wrsh t wrsl reset v bv a dd5x dd5x vdd
24 data sheet u17344ee1v1ds00 pd70f3178(a) 3.5.7 interrupt timing note: i = 10?0 figure 3-7: interrupt timing table 3-4: interrupt timing parameter symbol test conditions min. typ. max. unit nmi high-level width t nih analog filter 500 45 ns nmi low-level width t nil analog filter 500 45 ns intpi note high-level width t ith analog filter 500 45 ns intpi note low-level width t itl analog filter 500 45 ns t nih t nil nmi t ith t itl intpn
25 data sheet u17344ee1v1ds00 pd70f3178(a) 3.6 peripheral function characteristics 3.6.1 timer p notes: 1. m = 2?0, n = 1?0 2. f clk is the system clock frequency as specified in section 3.3.1 ?cpu clock? on page 18. figure 3-8: timer p characteristics table 3-5: timer p characteristics parameter symbol test conditions min. typ. max. unit tipmn note 1 high-level width t tiph 150+4/ f clk 45+4/f clk note 2 ns tipmn note 1 low-level width t tipl 150+4/ f clk 45+4/f clk note 2 ns t tiph t tipl tipn
26 data sheet u17344ee1v1ds00 pd70f3178(a) 3.6.2 csi b remark: n = 2?0 figure 3-9: csi slave mode characteristics table 3-6: csib master mode characteristics parameter symbol test conditions min. max. unit sckbn cycle time t kcy1 125 ns sckbn high level width t kh1 0.5 t kcy1 - 15 ns sckbn low level width t kl1 0.5 t kcy1 - 15 ns sibn setup time (to sckbn ) t sik1 30 ns sibn hold time (from sckbn ) t ksi1 25 ns delay time from sckbn to sobn t kso1 25 ns table 3-7: csib slave mode characteristics parameter symbol test conditions min. max. unit sckbn cycle time t kcy1 200 ns sckbn high level width t kh1 0.5 t kcy1 - 15 ns sckbn low level width t kl1 0.5 t kcy1 - 15 ns sibn setup time (to sckbn ) t sik1 50 ns sibn hold time (from sckbn ) t ksi1 50 ns delay time from sckbn to sobn t kso1 50 ns t kln t khn t kcyn input data t sikn t ksin output data t kson sckbn sibn sobn
27 data sheet u17344ee1v1ds00 pd70f3178(a) 3.6.3 uarta 3.6.4 i2c notes: 1. at the start condition, the first clock pulse is generated after the hold time. 2. the system requires a minimum of 300 ns hold time internally for the sda signal (at v ihmin of scl0 signal) in order to occupy the undefined area at the falling edge of scl0. 3. if the system does not extend the scl0 signal low hold time (t low ), only the maximum data hold time (t hd:dat ) needs to be satisfied. 4. the high-speed-mode iic bus can be used in a normal-mode iic bus system. in this case, set the high-speed-mode iic bus so that it meets the following conditions: - if the system does not extend the scl0n signal?s low state hold time: t su:dat ? 250 ns - if the system extends the scl0n signal?s low state hold time: transmit the following data bit to the sd a0 line prior to releasing the scl0 line (t rmax .+t su:dat = 1000 + 250 = 1250 ns: normal mode iic bus specification). table 3-8: uart characteristics parameter symbol test co nditions min. max. unit transfer rate t uarta 312.5 kbps table 3-9: characteristics i2c parameter symbol normal mode high-speed mode unit min. max. min. max. scl0 clock frequency f clk 0 100 0 400 khz bus-free time (between stop/start conditions) t buf 4.7 ? 1.3 ? s hold time note 1 t hd:sta 4.0 ? 0.6 ? s scl0 clock low-level width t low 4.7 ? 1.3 ? s scl0 clock high-level width t high 4.0 ? 0.6 ? s setup time for start/restart conditions t su:sta 4.7 ? 0.6 ? s data hold time cbus compatible master t hd:dat 5.0 ? ? ? s i2c mode 0 note 2 ? 0 note 2 0.9 note 3 s data setup time t su:dat 250 ? 100 note 4 ?ns stop condition setup time t su:sto 4.0 ? 0.6 ? s capacitive load of each bus line c b ? 50 ? 50 pf
28 data sheet u17344ee1v1ds00 pd70f3178(a) figure 3-10: i2c timing remarks: 1. p: stop condition 2. s: start condition 3. s r : restart condition 3.6.5 fcan table 3-10: afcan characteristics parameter symbol test co nditions min. max. unit transfer rate t fcan f peripheral t 16 mhz 1mbps scl0 p t su:sta t hd:sta t low t high t buf sda0 t sp t r t hd:dat t f t su:dat s tt hd:sta su:sto sr p
29 data sheet u17344ee1v1ds00 pd70f3178(a) 3.6.6 a/d converter (t a = -40 ~ +85c, bv dd5 = v dd5 = v avdd = 4.3 ~ 5.5 v, bv ss5 = v ss5 = av ss = 0 v) notes: 1. quantization error is not included 2. t conv depends on register ada0m1 figure 3-11: analog input equivalent circuit note: these are typical values only for reference. this values aren?t part of the mass production test. table 3-11: a/d converter characteristics parameter symbol test cond itions min. typ. max. unit resolution - 10 bit overall error note 1 - r 4lsb conversion time note 2 t conv 4.84 38.75 s analog input voltage v ian av ss av dd v analogue supply current i avdd 510ma ain r ~ 4.44 k ?
30 data sheet u17344ee1v1ds00 pd70f3178(a) 3.7 flash memory 3.7.1 basic characteristics (t a = -40 ~ +85c, bv dd5 = v dd5 = v avdd = 4.3 ~ 5.5 v, bv ss5 = v ss5 = av ss = 0 v) note: flmd0 is shared function of the mode pin. 3.7.2 serial write operation characteristics (t a = -40 ~ +85c, bv dd5 = v dd5 = v avdd = 4.3 ~ 5.5 v, bv ss5 = v ss5 = av ss = 0 v) note: flmd0 is shared function of the mode pin. figure 3-12: flash memory timing table 3-12: flash memory characteristics parameter symbol test conditions min. typ. max. unit operation frequency f cpu 432mhz number of rewrites c wrt 100 times high level input voltage v ih flmd0 note 0.8 bv dd bv dd v low level input voltage v il 0 0.2 bv dd v programming temperature t prg -40 +85 c table 3-13: flash memory characteristics parameter symbol test conditions min. typ. max. unit count start time from rising edge of reset to flmd0 note t rfcf t ost + 4500/ f osc ms count execution time t count 7800/f osc ms flmd0 counter high/low level width t ch ,t cl 1s rfcf 0 v dd v reset flmd1 (pdl5) flmd0 (mode) 0 v dd v 0 v dd v t count t cl t ch t f t r t
31 data sheet u17344ee1v1ds00 pd70f3178(a) 4. package drawing figure 4-1: package drawing detail of lead end q r s m a b cd f g h ij 75 76 51 50 100 1 26 25 k l m n p s s item millimeters s100gc-50-8eu-1 a b c d f g h i j k l m n p q r s 16 .0 0. 2 14 .0 0. 2 14 .0 0. 2 16 .0 0. 2 1. 00 1. 00 0. 08 0. 5 (t.p .) 1. 0 0. 2 0. 5 0. 2 0. 17 +0.03 -0.07 0. 08 0. 10 0. 05 3 +7 -3 1. 60 m a x 0. 22 +0.05 -0.04 1. 40 0. 05
32 data sheet u17344ee1v1ds00 pd70f3178(a) 5. recommended sol dering conditions solder this product under the following recommended conditions. for details of the recommended soldering conditions, refer to information document semiconductor device: mounting technology manual (c10535e). for soldering methods and conditions other than those recommended please consult nec. note: after that, prebaking is necessary at 125 c for 10 hours. the number of days refers to storage at 25c, 65% rh max after the dry pack has been opened. caution: do not use two or more soldering methods in combination (except partial heating method). table 5-1: soldering conditions soldering method soldering condition symbol of recommended soldering condition infrared reflow package peak temperature: 235 c, time: 10 seconds max., number of times: 3 max., number of days: 7 note ir35-107-3
33 data sheet u17344ee1v1ds00 pd70f3178(a) 6. revision history version date author remarks 0.1 2004/09/20 s.vollhardt first released version of this document 0.2 2004/10/05 s.vollhardt first official release s.vollhardt csib max speed for master & slave mode corrected s.vollhardt uarta max speed added s.vollhardt ac values added s.vollhardt flash write / erase time and flmd0 rise/fall time removed ee1v1 2005/02/25 s.vollhardt this version replaced the ?preliminary? one u17344ee1v0ds00. table 3-2, dc characteristics, pag e 19, the value of supply cur- rent i dd11 (max.) has been changed from 85 ma to 90 ma.
34 data sheet u17344ee1v1ds00 pd70f3178(a) notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
35 data sheet u17344ee1v1ds00 pd70f3178(a) the information in this document is current as of february 25, 2005. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec elect ronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ?
36 data sheet u17344ee1v1ds00 pd70f3178(a) regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics america inc. santa clara, california t el: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (europe) gmbh duesseldorf, germany t el: 0211-65 03 1101 fax: 0211-65 03 1327 sucursal en espa?a madrid, spain tel: 091- 504 27 87 fax: 091- 504 28 60 succursale fran?aise vlizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. singapore tel: 65-6253-8311 fax: 65-6250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 filiale italiana milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 branch sweden taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 united kingdom branch milton keynes, uk tel: 01908-691-133 fax: 01908-670-290
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